at28lv256 256k (32k x 8) low voltage cmos e 2 prom features fast read access time - 200 ns automatic page write operation internal address and data latches for 64-bytes internal control timer fast write cycle times page write cycle time: 10 ms maximum 1 to 64-byte page write operation low power dissipation 15 ma active current 20 m a cmos standby current hardware and software data protection data polling for end of write detection high reliability cmos technology endurance: 10,000 cycles data retention: 10 years single 3.3v 5% supply jedec approved byte-wide pinout commercial and industrial temperature ranges description the at28lv256 is a high-performance electrically erasable and programmable read only memory. its 256k of memory is organized as 32,768 words by 8 bits. manufactured with atmels advanced nonvolatile cmos technology, the device offers access times to 200 ns with power dissipation of just 54 mw. when the device is deselected, the cmos standby current is less than 200 m a. the at28lv256 is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 64-byte page register to allow writing of up to 64-bytes simultaneously. during a write cycle, the addresses and 1 to (continued) pdip, soic top view pin name function a0 - a14 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect dc dont connect pin configurations tsop top view 0273e note: plcc package pins 1 and 17 are dont connect. plcc top view at28lv256 2-145
block diagram 64-bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected a new access for a read or write can begin. atmels 28lv256 has additional features to ensure high quality and manufacturability. the device utilizes internal error correction for extended endurance and improved data retention characteristics. an optional software data protection mechanism is available to guard against inad- vertent writes. the device also includes an extra 64-bytes of e 2 prom for device identification or tracking. description (continued) temperature under bias................. -55c to +125c storage temperature...................... -65c to +150c all input voltages (including nc pins) with respect to ground ................... -0.6v to +6.25v all output voltages with respect to ground .............-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ................... -0.6v to +13.5v *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* 2-146 at28lv256
device operation read: the at28lv256 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either ce or oe is high. this dual- line control gives designers flexibility in preventing bus contention in their system. byte write: a low pulse on the we or ce input with ce or we low (respectively) and oe high initiates a write cy- cle. the address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. once a byte write has been started it will automatically time itself to completion. once a programming operation has been initiated and for the duration of t wc , a read operation will effectively be a poll- ing operation. page write: the page write operation of the at28lv256 allows 1 to 64-bytes of data to be written into the device during a single internal programming period. a page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. each successive byte must be writ- ten within 150 m s (t blc ) of the previous byte. if the t blc limit is exceeded the at28lv256 will cease accepting data and commence the internal programming operation. all bytes during a page write operation must reside on the same page as defined by the state of the a6 - a14 inputs. for each we high to low transition during the page write operation, a6 - a14 must be the same. the a0 to a5 inputs are used to specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. data polling: the at28lv256 features data polling to indicate the end of a write cycle. during a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be pre- sented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at anytime during the write cycle. toggle bit: in addition to data polling the at28lv256 provides another method for determining the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 toggling be- tween one and zero. once the write has completed, i/o6 will stop toggling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. data protection: if precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply. atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. hardware protection: hardware features protect against inadvertent writes to the at28lv256 in the follow- ing ways: (a) v cc power-on delay - once v cc has reached 1.8v (typical) the device will automatically time out 10 ms (typical) before allowing a write: (b) write inhibit - holding any one of oe low, ce high or we high inhibits write cy- cles; (c) noise filter - pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a write cycle. software data protection: a software-control- led data protection feature has been implemented on the at28lv256. software data protection (sdp) helps pre- vent inadvertent writes from corrupting the data in the de- vice. sdp can prevent inadvertent writes during power-up and power-down as well as any other potential periods of system instability. the at28lv256 can only be written using the software data protection feature. a series of three write commands to specific addresses with specific data must be presented to the device before writing in the byte or page mode. the same three write commands must begin each write opera- tion. all software write commands must obey the page mode write timing specifications. the data in the 3-byte command sequence is not written to the device; the ad- dress in the command sequence can be utilized just like any other location in the device. any attempt to write to the device without the 3-byte se- quence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , read operations will effectively be polling operations. device identification : an extra 64-bytes of e 2 prom memory are available to the user for device identification. by raising a9 to 12v 0.5v and using ad- dress locations 7fc0h to 7fffh the additional bytes may be written to or read from in the same manner as the regu- lar memory array. at28lv256 2-147
symbol parameter condition min max units i li input load current v in = 0v to v cc + 1v 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i sb v cc standby current cmos ce = v cc - 0.3v to v cc + 1v com. 20 m a ind. 50 m a i cc v cc active current f = 5 mhz; i out = 0 ma 15 ma v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 1.6 ma 0.3 v v oh output high voltage i oh = -100 m a 2.0 v dc characteristics at28lv256-20 at28lv256-25 operating temperature (case) com. 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c v cc power supply 3.3v 5% 3.3v 5% dc and ac operating range mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z chip erase v il v h (3) v il high z 3. v h = 12.0v 0.5v. notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. operating modes 2-148 at28lv256
ac read characteristics at28lv256-20 at28lv256-25 symbol parameter min max min max units t acc address to output delay 200 250 ns t ce (1) ce to output delay 200 250 ns t oe (2) oe to output delay 0 80 0 100 ns t df (3, 4) ce or oe to output float 0 55 0 60 ns t oh output hold from oe, ce or address, whichever occurred first 00ns notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read waveforms (1, 2, 3, 4) t r , t f < 20 ns input test waveforms and measurement level output test load typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v note: 1. this parameter is characterized and is not 100% tested. pin capacitance (f = 1 mhz, t = 25c) (1) at28lv256 2-149
symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width ( we or ce) 200 ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 0 ns t dv time to data valid nr (1) note: 1. nr = no restriction ac write characteristics ac write waveforms we controlled ce controlled 2-150 at28lv256
symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 200 ns t blc byte load cycle time 150 m s t wph write pulse width high 100 ns page mode characteristics software protected write cycle waveforms (1, 2, 3) notes: 1. a0 - a14 must conform to the addressing sequence for the first three bytes as shown above. 2. a6 through a14 must specify the same page address during each high to low transition of we (or ce) after the software code has been entered. 3. oe must be high only when we and ce are both low. load last byte to last address (3) load data a0 to address 5555 load data 55 to address 2aaa load data aa to address 5555 notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. data protect state will be re-activated at the end of program cycle. 3. 1 to 64-bytes of data are loaded. enter data protect state writes enabled (2) programming algorithm load data xx to any address (3) at28lv256 2-151
symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns toggle bit characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. symbol parameter min typ max units t dh data hold time 0 ns t oeh oe hold time 0 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns data polling characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. toggle bit waveforms notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling waveforms 2-152 at28lv256
at28lv256 2-153
t acc (ns) i cc (ma) ordering code package operation range active standby 200 80 0.2 at28lv256-20jc 32j commercial at28lv256-20pc 28p6 (0 c to 70 c) at28lv256-20sc 28s at28lv256-20tc 28t 80 0.2 at28lv256-20ji 32j industrial at28lv256-20pi 28p6 (-40 c to 85 c) at28lv256-20si 28s at28lv256-20ti 28t 250 80 0.2 AT28LV256-25JC 32j commercial at28lv256-25pc 28p6 (0 c to 70 c) at28lv256-25sc 28s at28lv256-25tc 28t 80 0.2 at28lv256-25ji 32j industrial at28lv256-25pi 28p6 (-40 c to 85 c) at28lv256-25si 28s at28lv256-25ti 28t note: 1. see valid part number table below. ordering information (1) package type 32j 32 lead, plastic j-leaded chip carrier (plcc) 28p6 28 lead, 0.600" wide, plastic dual inline package (pdip) 28s 28 lead, 0.300" wide, plastic gull wing small outline (soic) 28t 28 lead, plastic thin small outline package (tsop) the following table lists standard atmel products that can be ordered. device numbers speed package and temperature combinations at28lv256 20 jc, ji, pc, pi, sc, si, tc, ti at28lv256 25 jc, ji, pc, pi, sc, si, tc, ti valid part numbers 2-154 at28lv256
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